The present invention relates generally to integrated circuits, and, more particularly, to a power management system for an integrated circuit.
Integrated circuits (ICs) including system-on-chips (SoCs) integrate various digital and sometimes also analog components on a single chip. Many ICs further include different power domains such as high and low power domains. The high power domain includes components that operate when the IC is in a high power mode and powered down when the IC is in a low power mode. The low power domain includes components that operate when the IC is in the high and low power modes. ICs with multiple power domains require multiple supply voltages that are provided by multiple voltage regulators. The high power domain is served by a high power voltage regulator (hereinafter referred to as a “full-power regulator”) and the low power domain is served by a low power voltage regulator (hereinafter referred to as a “low-power regulator”). The low-power regulator is operational when the IC is in the low power mode and hence, the low-power regulator is designed to consume less power than the full-power regulator.
Such ICs also include a power management controller (PMC) that monitors the operating voltage of the IC. The PMC includes voltage monitoring circuits such as low-voltage detection (LVD) and high-voltage detection (HVD) circuits. The LVD circuits monitor the operating voltage of the IC and compare it with an LVD threshold voltage. The LVD threshold voltage represents the lowest voltage level at which the IC can operate without failing or deviating from the functional specification of the IC. Therefore, when the operating voltage drops below the LVD threshold voltage, the LVD circuit generates a safe-state signal to configure the IC in a reset or safe-state mode. Similarly, the HVD circuit configures the IC in the reset or safe-state mode when the operating voltage exceeds an HVD threshold voltage, in order to prevent the over-voltage condition from damaging the IC.
The above-mentioned voltage regulators and voltage monitoring circuits operate using reference voltage signals received from bandgap voltage reference generators. A bandgap voltage reference generator (hereinafter referred to as “bandgap generator”) is a reference voltage circuit that outputs a reference voltage signal at a fixed voltage level irrespective of environmental changes such as ambient temperature changes, power supply variations and load variation. Generally, the low-power regulator and voltage monitoring circuits receive a first reference voltage signal from a low-power bandgap generator and the full-power regulator receives a second reference voltage signal from a full-power bandgap generator. The low-power regulator and voltage monitoring circuits are operational when the IC is in the low power mode. Therefore, the low-power bandgap generator also is operational when the IC is in the low power mode and hence, the low-power bandgap generator is designed to consume less power than the full-power bandgap generator.
FIG. 1 shows an IC 100 operable in high and low power modes and that has a conventional power management system 101. The power management system 101 includes a low-power bandgap generator 102 and first circuitry 104. When the IC 100 is in either the high or low power mode, the low-power bandgap generator 102 generates and provides a low-power bandgap reference voltage signal (VLPBG—REF) to the first circuitry 104. The first circuitry 104 includes a low-power regulator (not shown) and voltage monitoring circuits (not shown) such as LVD and HVD modules. For example, the first circuitry 104 may include an LVD module 106. The LVD module 106 receives the low-power bandgap reference voltage signal (VLPBG—REF) that is at a voltage level of a LVD threshold voltage and a supply voltage (VSUPPLY) indicative of an operating voltage of the IC 100, and outputs an LVD signal (high active) when the supply voltage (VSUPPLY) is greater than the low-power bandgap reference voltage signal (VLPBG—REF). To ensure proper operation of the LVD module 106, the LVD threshold voltage is designed to lie within a designated voltage range. When the IC 100 is powered on after a power-on-reset (POR), the low-power bandgap generator 102 is in an untrimmed condition for a first predetermined time period after the POR and hence, the accuracy of the low-power bandgap reference voltage signal (VLPBG—REFF) is low. The low-power bandgap generator 102 is trimmed and the low-power bandgap reference voltage signal (VLPBG—REF) is stabilized after the first predetermined time period after the POR.
During the first predetermined time period, the low-power bandgap reference voltage signal (VLPBG—REF) is unstable and has low accuracy and hence, may not be within the designated voltage range. Thus, the LVD module 106 may not assert when the supply voltage (VSUPPLY) is less than the LVD threshold voltage, which could cause a failure or deviation from the functional specification of the IC 100. Further, low-power consumption requirements of the IC 100 constrain the efforts to design a high accuracy low-power bandgap generator. Designing an improved low-power bandgap generator 102 is difficult and requires additional components that result in an increase in the area overhead, power consumption and cost of production.
FIG. 2 shows an IC 200 operable in high and low power modes and that includes a conventional power management system 201. The power management system 201 includes a full-power bandgap generator 202, a soft-start circuit 204 connected to the full-power bandgap generator 202, a first multiplexer 206 connected to the soft-start circuit 204 and the full-power bandgap generator 202, and a full-power regulator 208 connected to the first multiplexer 206. When the IC 200 transitions from low power mode to high power mode, the full-power regulator 208 is powered on and operates in a voltage build-up phase. The full-power bandgap generator 202 is powered on and generates a full-power bandgap reference voltage signal (VFPBG—REF). The soft-start circuit 204 receives the full-power bandgap reference voltage signal (VFPBG—REF), and outputs an intermediate reference voltage signal (VINT—REF) having a controlled ramp-up rate. The first multiplexer 206 receives and outputs the intermediate reference voltage signal (VINT—REF) to the full-power regulator 208 when the full-power regulator 208 is in the voltage build-up phase.
When the voltage level of the intermediate reference voltage signal (VINT—REF) exceeds a first threshold voltage level, the soft-start circuit 204 generates a soft-start complete signal (VSOFT—START—COMPLETE) to indicate the completion of the voltage build-up phase. The first multiplexer 206 receives the soft-start complete signal (VSOFT—START—COMPLETE) at a select terminal thereof and outputs the full-power bandgap reference voltage signal (VFPBG—REF) to the full-power regulator 208. The full-power regulator 208 receives the full-power bandgap reference voltage signal (VFPBG—REF) and starts operating in a full-regulation phase. The full-power regulator 208 reaches a stable operation state in the full-regulation phase. Thus, when the IC 200 transitions from low power mode to high power mode, the full-power regulator 208 starts operating in the voltage build-up phase only when the full-power bandgap generator 202 is powered on. The time required for the IC 200 to transition from the low power mode to the high power mode is defined as a low power wake-up time. Since the full-power regulator 208 waits for the full-power bandgap generator 202 to be powered on, the low power wake-up time of the IC 200 increases. Thus, the performance of the IC 200 is affected.
It would be advantageous to have a power management system for an integrated circuit that provides accurate reference voltage to voltage regulators and voltage monitoring circuits to the integrated circuit, prevents damage and improves the performance of the integrated circuit, and overcomes the above-mentioned limitations of conventional power management systems.